The ADVANTEST D3286 is currently in stock and available for purchase on our  Sales Page
It is also available for immediate rental.
Custom-Cal has a high success rate in the repair of the ADVANTEST D3286. A calibration by Custom-Cal is performed by engineers with extensive OEM experience. We have the expertise and the necessary standards to perform the ADVANTEST D3286 Calibration, onsite calibration may be available. We specialize in quick turnaround times and we can handle expedited deliveries upon request.

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   ADVANTEST D3286   Description / Specification:    
ADVANTEST D3286 12 G-bps Error Detector

The Advantest D3286 12G-bps error detector is provided with powerful evaluation and analysis functions includ ing the burst data (noncontinuous data) measurement function, the error-generating bit location function, the error measurement function for the specified bit range and the mixed SDH pattern synchronization function . (Mixed SDH pattern is generated by the D3186 and transferred under real conditions.) SDH/SONET Frame Synchronization Suitable for System Evaluation. With SDH/SONET equipment. frames are recognized by means of the synchronization pattern described on the SDH (section overhead). The D3286 error detector mounts the circuit for recognizing the frame synchronization signal and has the capability to set not only SDH/SONET frames but also FDDI and ATM frames and arbitrary synchronization patterns, allowing frames to be synchronized with user-specific frame patterns. The Advantest D3286 is provided with the error location function to locate error bits. For this reason , system errors occurring because of frequency characteristics of the circuit can be easily detected. When this function is used together with the error interval function to identify the cause of random errors, rapid improvement and evaluation are made possible. Specifications. Clock input Frequency range: 150 MHz to 12.0 GHz. DATA input; Frequency range: 150 Mbps to 12.0 Gbps. Sensitivity: 100 mVp-p typ. (12 Gbps), 50 mVp-p typ. (6 Gbps), Approx. 50 ohms.Measurable patterns; PRBS (pseudo random pattern) : 2^N-1, N = 7, 9, 10, 11, 15, 23 and 31. WORD (programmable pattern): Max. 8-Mbit long. SDH/SONET pattern: Max. STM-64/STS-192. Options: OPT3286+70: Mixed pattern generation function.


Standard Calibration $670.00 *
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*This is a Web introductory price for one calibration of the ADVANTEST D3286. Price does not in most cases include measurement performance data. Pricing does include NIST traceable calibration and issue of a calibration certificate and calibration label. Pricing may vary slightly due to volume and location of laboratory supporting calibration. Volume pricing may apply. On-site fees may apply depending on logistics, location and volume of work to be completed during the visit.

Related Communication Terms and Definitions. For a complete list go to our  Terms and Definitions Page.

Bandwidth is the difference between the upper and lower frequencies in a contiguous set of frequencies within which a fiber optic component, link or network will operate.

Multimode Fiber
Multimode Fiber has a large core (almost always 62.5 microns - a micron is one one millionth of a meter - but sometimes 50 microns) and is used with LED sources at wavelengths of 850 and 1300 nm for short distance, lower speed networks like LANs. Both multimode and singlemode fiber have an outside diameter of 125 microns - about 5 thousandths of an inch - just slightly larger than a human hair.

Synchronous Digital Hierarchy (SDH) is an international digital telecommunications network hierarchy which standardises transmission around the bit rate of 51.84 megabits per second, which is also called STS-1. Multiples of this bit rate comprise higher bit rate streams. Thus STS-3 is 3 times STS-1, STS-12 is 12 times STS-1, and so on. STS-3 is the lowest bit rate expected to carry ATM traffic, and is also referred to as STM-1 (Synchronous Transport Module-Level 1). The SDH specifies how payload data is framed and transported synchronously across optical fibre transmission links without requiring all the links and nodes to have the same synchronized clock for data transmission and recovery.

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