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The Agilent 16950A 68 Channel 4 GHz Timing/600 MHz State Logic Analysis Module is compatible with the 16900 Series mainframes. Specifications. State speed: 600 MHz. Max data rate: 600 Mb/s (DDR), 800 Mb/s (Dual sample). Memory depth: 256 K to 64 M. Minimum eye width in system under test: 600 ps typical. Minimum time between active clock edges: 1.67 ns (600 Mb/s state mode). Minimum state clock pulse width: 1.67 ns. Timing analysis sample rate: 4 GHz. Time interval accuracy Within a pod pair: ± (1.0 ns + 0.01% of time interval reading). Time interval accuracy Between pod pairs: ± (1.75 ns + 0.01% of time interval reading). Timing zoom Memory depth: 64 K samples. Trigger position: Start, center, end, or user-defined. Minimum data pulse width: 750 ps.
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