Keysight (Agilent) M9703B CALIBRATION and Keysight (Agilent) M9703B REPAIR

 
A calibration by Custom-Cal is performed by engineers with extensive OEM experience. We have the expertise and the necessary standards to perform the Keysight (Agilent) M9703B Calibration, onsite calibration may be available. We specialize in quick turnaround times and we can handle expedited deliveries upon request.

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   Keysight (Agilent) M9703B   Description / Specification:    
Keysight (Agilent) M9703B 12-bit, 3.2 GS/s, 8 Ch, AXIe High-Spd Digitizer/Wideband Rec

The Keysight M9703B is an 8-channel, 12-bit wideband digital receiver/digitizer that is able to capture signals from DC up to 2 GHz at 1.6 GS/s, with exceptional measurement accuracy. An interleaving capability allows two channels to be combined to acquire at 3.2 GS/s on four channels, with up to 1.4 GHz instantaneous bandwidth. It also provides up to 16 GB of DDR3 acquisition memory and real-time data processing capability with four Xilinx Virtex-6 FPGAs. The on-board FPGAs can feature an optional real-time digital down-converter (DDC) that allows tuning and zooming on the signal to be analyzed. This DDC functionality improves the dynamic range, reduces the noise floor, extends the capture time, and accelerates measurement speed.
Specifications.

Analog Input (IN1 to IN8 SMA Connectors).
Number of channels: 8 (without -INT option), 8 or 4 (with -INT option).
Impedance: 50 Ω ±2 %.
Coupling: DC.
Full scale ranges (FSR): 1 V and 2 V (3.98 dBm and 10 dBm).
Maximum input voltage;
  1V FSR: Clamp at ± 3.6 V, absolute maximum DC voltage rating ± 4.6 V.
  2V FSR: Clamp at ± 6.3 V, absolute maximum DC voltage rating ± 5.0 V.
Input frequency range (-3 dB bandwidth): DC to 650 MHz (typical)(-F05), DC to 1.9 GHz (typical) in 1V FSR at 1 GS/s or 1.6 GS/s(-F10).
DC gain accuracy: ±0.5% (typical).
Offset accuracy: ±0.5% in 1V FSR, ±1.5% in 2V FSR.
Input voltage offset: -2xFSR to +2xFSR.
Bandwidth limit filters: 650 MHz (nominal).
Frequency response flatness: ±1 dB from DC to 650 MHz.

Options.
SR1, 1 GS/s sampling rate version (2 GS/s sampling rate with -INT option).
SR2, 1.6 GS/s sampling rate version (3.2 GS/s sampling rate with -INT option).
F05, Input Frequency: DC to 650 MHz.
F10, Input Frequency: DC to 2 GHz (non-interleaved).
M10, 1 GB (64 MSample/ch) acquisition memory.
M40, 4 GB (256 MSample/ch) acquisition memory.
M16, 16 GB (1 GSample/ch) acquisition memory.
DGT, Digitizer firmware.
DDC, Wideband real-time digital down-conversion.
INT, Interleaved channel sampling functionality.
FDK, FPGA programming access.
TSR, Triggered simultaneous acquisition and readout.



 



Related Bench Equipment Terms and Definitions. For a complete list go to our  Terms and Definitions Page.

dBc
dBc (decibels relative to the carrier) is the power ratio of a signal to a carrier signal, expressed in decibels. If the dBc figure is positive, then the relative signal strength is greater than the carrier signal strength. If the dBc figure is negative, then the relative signal strength is less than carrier signal strength.

Load Regulation
Load regulation is the capability to maintain a constant voltage (or current) level on the output channel of a power supply despite changes in the supply's load (such as a change in resistance value connected across the supply output).

Power Linearity
When changing the power level and measuring the differences (in dB) between actual and displayed power levels, the power linearity is ± half the span (in dB) between the maximum and the minimum value of all differences.

Settling Time
Settling time of an output device is the time elapsed from the application of an ideal instantaneous step input to the time at which the amplifier output has entered and remained within a specified error band, usually symmetrical about the final value.


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