Used AGILENT N4903A Buy / Purchase at the right Price.
Custom-Cal has a used AGILENT N4903A J-BERT High-Performance Serial BERT in stock and ready for purchase at a fair price. All units sold by Custom-Cal are provided with an applicable NIST traceable calibration/performance verification and a 90 day warranty (unless otherwise noted). With this added service, you can be confident that you are buying a fully functional unit that meets OEM specifications.

We are always willing to work with the customer on price. If you would like to buy a used AGILENT N4903A but, don't see the price you want, please name your price below and we will try to find one for you to purchase.
AGILENT N4903A J-BERT High-Performance Serial BERT


General description of the used AGILENT N4903A for sale.
Agilent J-BERT N4903A High-Performance Serial BERT. Key Capabilities: Integrated and calibrated jitter sources: PJ, SJ, RJ, BUJ, ISI and sinusoidal interference. Jitter tolerance testing: PCI Express®, SATA, DisplayPort, Fibre Channel, FB-DIMM, CEI, 10 GbE, XFP/XFI, SFP+. Quick eye masks and BER contours. Bit recovery mode for analyzing undeterministic patterns. SSC generation. CDR with tunable loop bandwidth for compliant measurements for all data rates. Pattern sequencer and capture to simplify the handling of complex data patterns. Subrate clock outputs. Pattern generator options. J-BERT key characteristics: 150 Mb/s to 7 Gb/s or 12.5 Gb/s - enough margin for characterizing today’s most popular serial interfaces. Calibrated and integrated jitter injection (opt. J10). All in one box: RJ, PJ, BUJ, ISI, sinusoidal interference to stress the receiver with > 50 % eye closure. Automated and compliant jitter tolerance tests covers popular serial bus standards: PCI Express, SATA, Fibre Channel, SATA, FB-DIMM, CEI 6G/11G, 10 GbE/XAUI, XFP/XFI, SFP+. Delay control input for generator to apply any external jitter source. Bit recovery mode to test unknown data traffic. Pattern sequencer to generate complex training sequences. SSC clocking for computer buses. Subrate clocks to generate reference clocks easily. Differential I/O for DATA and CLOCK and most supplementary signals for testing serial interfaces. Integrated CDR (clock data recovery) to test clockless devices from 1 to 12.5 Gb/s. Compliant and tunable loop bandwidth (opt. CTR). Highest performance BERT for accurate measurements. Remote operation of GUI via web server.

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